Senior Field-Programmable Gate Arrays Designer

About the role

We are looking for a senior engineer to lead the development and testing of complex FPGA projects using VHDL/Verilog. The role involves designing hardware architectures, implementing digital signal processing algorithms, and delivering software‑defined radio solutions for advanced RF applications.

Key responsibilities

• Develop and test complex VHDL/Verilog projects on FPGA platforms.
• Participate in hardware architecture design and early trade‑off studies.
• Develop and verify DSP algorithms using Python or MATLAB.
• Design, simulate, code and verify SDR projects in FPGAs and DSPs, including JESD204B/C, 10G/100G Ethernet, FFT, DDC/DUC, filtering and signal generators.
• Perform timing and area optimizations of FPGA designs.
• Assist in hardware bring‑up, troubleshooting and integration.
• Operate RF test equipment such as signal generators, spectrum analyzers and network analyzers.
• Create automated test suites for software‑defined radio devices.

Required profile

• B.Sc. or higher in Electronic Engineering, Computer Science or a related field.
• 10+ years of hands‑on experience with FPGA design and verification.
• Proven track record in VHDL or Verilog programming.
• Strong communication skills in English (upper‑intermediate).
• Passion for electronics, willingness to learn new challenges and ability to work under pressure.

Required skills

• VHDL
• Verilog
• Xilinx Vivado
• Altera/Intel Quartus
• ModelSim
• Linux (user)
• Bash scripting
• TCL scripting
• Python
• MATLAB
• FPGA design and timing/area optimization
• Digital signal processing (DSP) algorithms
• JESD204B/C interfaces
• 10G/100G Ethernet
• FFT, DDC/DUC, filtering
• RF test equipment (signal generators, spectrum analyzers, network analyzers)

What we offer

• Salary approximately $10,500 per month (paid in AED).
• Full relocation support to Abu Dhabi, UAE.
• Collaborative culture with state‑of‑the‑art facilities.
• Competitive compensation and growth opportunities.